The present invention relates to a clock pulse generator suitable for use in a semiconductor integrated circuit.
A conventional clock pulse generator for a semiconductor integrated circuit receives a sinusoidal signal having a small amplitude of about 400 mVpp from an external signal source through an input capacitor. An amplifier in which the input and output of an inverter is bridged with a high resistor, amplifies the sinusoidal signal. This type of amplifier has nonlinear amplification characteristics that an amplification factor in the neighborhood (at xc2xd of a normal source voltage in the case of a CMOS) of a threshold level (threshold value) is maximum and an amplification factor thereof also decreases as it deviates from the threshold value.
The sinusoidal signal is vibrated and amplified by the amplifier with a level (corresponding to a threshold value in the case of the CMOS) equal to one-half the source voltage as the center. The output signal amplified in this way is waveform-shaped by a pulse-shaping inverter, after which it is outputted as a clock signal.
A prior art has been also disclosed wherein three clock trees are used in a sync signal generator to prevent a malfunction based on a noise burst contained in the sinusoidal signal and thereby reliably complement a data signal (U.S. Pat. No. 6,005,412).
However, a power supply line and an earth line to which the semiconductor integrated circuit is connected, have generally been contaminated by digital noise produced by the semiconductor integrated circuit per se or its peripheral digital circuit. The digital noise is superimposed on a sinusoidal signal of small amplitude. The digital noise described herein is called fine noise superimposed on the power supply line or earth line due to a transient response caused by the rising edge or falling edge of a pulse signal.
The digital noise is also amplified by the amplifier. The digital noise is extremely and widely amplified in the neighborhood of the threshold value of the inverter in particular. Thus, when the level of the digital noise exceeds a predetermined level, a pulse shaping inverter is turned on and off due to the digital noise within one cycle of the sinusoidal signal. As a result, a problem to be solved still remains that an improper clock pulse is produced.
A clock pulse generator according to the present invention includes an input terminal, an input bias setting circuit, a threshold addition circuit, a threshold subtraction circuit and a pulse combining circuit. The input bias setting circuit adds a predetermined bias voltage to the sinusoidal signal delivered from the input terminal so as to generate an addition sinusoidal signal. The threshold voltage addition circuit shapes the addition sinusoidal signal in addition to a first threshold voltage so as to generate a first pulse signal. The threshold voltage subtraction circuit shapes the addition sinusoidal signal in subtraction to a second threshold voltage so as to generate a second pulse signal. The pulse combining circuit synchronizes either one of rising or falling edges of the first clock pulse with those of the second clock pulse so as to generate an output clock pulse.